Digital SOC Architect

Digital SOC Architect

Introduction

At Blue Origin, we envision millions of people living and working in space for the benefit of Earth. We’re working to develop reusable, safe, and low-cost space vehicles and systems within a culture of safety, collaboration, and inclusion.

Job Summary

We are seeking a Digital SOC Architect/Engineer to design and develop critical components for our space-based communications network. The ideal candidate brings expertise in digital architecture, RTL design, and system integration, thriving in a fast-paced environment where innovation meets mission-critical execution.

Responsibilities

• Design and develop digital hardware architectures for high-throughput satellite communications ASICs
• Create and implement RTL code for critical SOC blocks and interfaces
• Contribute to architecture optimization for performance, power, and area trade-offs
• Develop implementations for networking protocols and digital signal processing algorithms
• Collaborate with verification engineers to ensure robust and reliable designs
• Support FPGA prototype development for early validation
• Work with backend teams throughout the physical implementation process
• Document design specifications, architecture decisions, and implementation details
• Participate in design reviews and technical discussions with cross-functional teams
• Troubleshoot and debug complex digital design issues
• Optimize designs for timing, power, and area constraints
• Implement interfaces between digital hardware and firmware/software components
• Research and evaluate new architectural approaches to meet evolving requirements

Minimum Qualifications

• B.S. degree in Electrical Engineering, Computer Engineering, or related field
• 5+ years of experience in digital design and SOC architecture
• Proficiency in SystemVerilog or Verilog for RTL implementation
• Experience with SOC integration and interface design
• Understanding of digital timing and synchronization concepts
• Knowledge of industry-standard bus protocols (AXI, AHB, etc.)
• Familiarity with synthesis tools and RTL-to-gates methodology
• Experience with simulation and debugging of complex digital systems

Preferred Qualifications

• M.S. or Ph.D. in relevant engineering discipline
• Experience with high-speed networking hardware design (10G or above)
• Background in digital signal processing